One of the main aspect that come to our mind when selecting a mobile or computer is memory. Memory plays a vital role in today’s industry. The plethora of connected digital devices increases the amounts of data produced. To store and process such huge data, we need a large amount of memory which concurrently increases the cost and power. Looking back, some decades ago there was no mobile with on board memory and size of hard disks was bulky and costly too. Toshiba introduced planar NAND flash otherwise called as 2D NAND flash technology in 1989 with 400nm cells. This technology was the boot up of solid state drives, thumb drives, onboard mobile memories. Toshiba continuously reduced size of cell from 400nm every year. In 2006, size of single cell was 40nm i.e. ten times smaller than the first one. With the development of Multi Level Cell (MLC) and Triple Level Cell (TLC), size of storage devices reduced drastically.
(1) The size of memory can never be further increased as it consumes more space.
(2) Current 2D planar cell size is 15nm i.e. size of each transistor is 15nm which causes the electrons to be easily relocated to nearby cells because of more density.
So Toshiba found a solution with this 3D planar floating gate memory technology. Internal construction of planar based memory is like storing data in a single layer plane or like single storey building. Instead of doing that Toshiba decided to build memory with 48 layers vertically placed on above one which looks like a 48 storey building. So we get three times more density than planar technology with little bigger 30nm, 40nm and 50nm cells. Smart phone giant Samsung’s V-NAND called as Vertical NAND memory also resembles the same in construction with only 32 layers.
Semiconductor giant Intel and Micron signed an agreement to build 25nm based 3D NAND flash memory that they call as 3D cross-point (X point) technology. With this technology we can extend the capacity up to 10 Tera Bytes with more reduced size. Micron decided to use Multi Level Cells (MLC) which makes a single silicon wafer to have a maximum of 4 Tera Bytes of memory space but in future we can expect more with Triple Level Cells (TLC). Memory chips with 3D NAND flash will reach the market by end of this year. By deploying this technology we can expect that a thumb drive can have a capacity of 2 Tera bytes and memory cards have a capacity of 384 Giga bytes. Thus we came closer to the end of memory architecture era by reaching peak transistor count what Moore’s graph tells. But researches have been going on for deploying single molecule transistors in Integrated circuits which might overcome the Moore’s limit as the size of single molecule is 5nm.
About 3D planar by Micron: